NJU26220 - 1 - ver.2005-12-01 dolby virtual speaker / dolby headphone decoder general description the NJU26220 simulates a highly realistic 5.1-speaker surround sound listening environment from as few as two speakers or headphone by dolby virtual speaker/dolby headphone technology. the NJU26220 processes the dolby virtual speaker and dolby headphone technology that combined with pro logic ii processing. it includes pro logic ii decoder. moreover, multi-channel signal inputs from an external decoder are possible. it is suitable for digital tvs, stereo mini-components, pcs, and any audio/visual products. features ? dolby virtual speaker ? dolby headphone ? dolby pro logic ii (max 5.1ch output) ? multi-channel signals input (max 5.1ch input) ? monitor output ? lip-sync delay function (digital audio delay) digital signal processor specification ? 24bit fixed-point digital signal processing ? maximum clock frequency : 12.288mhz(standard), built-in pll circuit ? digital audio interface : 4 input ports / 4 output ports ? microcomputer interface : i 2 c bus (standard-mode/100kbps, fast-mode/400kbps ) : 4-wire serial bus (4-wire: clock, enable, input data, output data) ? power supply : dsp core : 1.8v : i/o interface: 3.3v(+5.0v input tolerant) ? package : qfp48-n2 (pb-free) package NJU26220fn2
NJU26220 - 2 - ver.2005-12-01 dsp block diagram timing generator / pll program control alu 24-bit x 24-bit multiplier address generation unit firmware rom data ram serial host interface general i/o interface sdo0 sdo2 sdo3 scl/sck sda/sdout ad1/sdin ad2/ssb clk clkout resetb 24bit fixed-point dsp core sdi* lri bcki mck bcko lro monitor c/sw sl/sr serial audio interface NJU26220 sdo1 l/r wdc sel muteb proc fig.1 NJU26220 block diagram function diagram NJU26220 features overview input trimmer dolby virtualspeaker dolby headphone dvs/dh stereo bypass mode, bypass mode sw3 l/r c/sw sl/sr c/sw l/r sl/sr sw2 l/r c/sw sl/sr moniitor downmix l/r sdi0 sdi1 sdi3 sl/sr sdi2 c/sw plii delay (c, sl/sr) prologic ii watchdog output wdc noise generator sdo1 sdo2 sdo3 sdo0 l/r c/sw sl/sr moniitor monitor out trimmer output trimmer (master & l/r/c/sl/sr/sw) output delay (c, sl/sr or l/r) sw1 sw1 : plii on/off sw2 : dvs/dh on/off sw3 : dvs/dh output mode select sw1 c/sw l/r sl/sr lfe generator l/r c/sw sl/sr fig.2 NJU26220 function diagram
NJU26220 - 3 - ver.2005-12-01 pin configuration 48 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 resetb test1 vddpll vsspll vss vdd clkout clk vddio vssio test2 test3 lri sdi0 sdi1 sdi2 sdi3 vdd vss vddio sdo0 sdo1 sdo2 sel vssio vddio proc wdc muteb test0 vdd vss vssio bcki vddio ad1/sdin ad2/ssb scl/sck sda/sdout vdd vss vssio vddio mck bcko lro sdo3 NJU26220 vssio fig.3 pin configuration
NJU26220 - 4 - ver.2005-12-01 pin description table1 pin description pin no. symbol i/o function 1 vddio p i/o power supply +3.3v 2 bcki i bit clock input 3 vssio g i/o power supply gnd 4 vss g dsp core power supply gnd 5 vdd p dsp core power supply +1.8v 6 test0 i* for test (connect with vssio through 3.3-ohm resistance.) 7 muteb i* master volume status afte r reset ?1?: 0db, ?0?: mute 8 wdc od* watchdog clock output pin (open-drain output) 9 proc i* signal processing after reset ?1?:normal processing, ?0?: waiting for a command without processing 10 vssio g i/o power supply gnd 11 vddio p i/o power supply +3.3v 12 sel i host interface selection ?1?: serial inte rface, ?0?: i 2 c bus 13 vddpll p pll power supply +1.8v 14 vsspll g pll power supply gnd 15 vss g dsp core power supply gnd 16 vdd p dsp core power supply +1.8v 17 clkout o osc clock output 18 clk i osc clock input (12.288mhz) 19 vssio g i/o power supply gnd 20 vddio p i/o power supply +3.3v 21 resetb i reset (rese tb=?0?: dsp reset) 22 test1 i for test (connect to vddio) 23 test2 i for test (connect to vssio) 24 test3 i for test (connect to vssio) 25 ad1/sdin i i 2 c address (i 2 c mode) / serial in (4-wire serial mode) 26 ad2/ssb i i 2 c address (i 2 c mode) / serial enable (4-wire serial mode) 27 scl/sck i i 2 c scl (i 2 c mode) / serial clock (4-wire serial mode) 28 sda/sdout i/o i 2 c sda (i 2 c mode) / serial out (4-wire serial mode) 29 vdd p dsp core power supply +1.8v 30 vss g dsp core power supply gnd 31 vssio g i/o power supply gnd 32 vddio p i/o power supply +3.3v 33 mck o a/d, d/a clock output (buffer output of a clk pin) 34 bcko o bit clock output 35 lro o lr clock output 36 sdo3 o audio data output ch.3 (surround channel (ls/rs) output) 37 sdo2 o audio data output ch.2 (center/s ub woofer channel (c/sw) output) 38 sdo1 o audio data output ch.1 (front channel (l/r) output) 39 sdo0 o audio data output ch.0 (monitor output) 40 vddio p i/o power supply +3.3v 41 vssio g i/o power supply gnd 42 vss g dsp core power supply gnd 43 vdd p dsp core power supply +1.8v 44 sdi3 i audio data input ch.3 45 sdi2 i audio data input ch.2 46 sdi1 i audio data input ch.1 47 sdi0 i audio data input ch.0 48 lri i lr clock input note1: i: input, o: output, od: open-drain output, i/o: bidirectional, p: +power, g: gnd note2: i/o with * operate as bidirectional pins when test . connect with vddio or vssio through 3.3k-ohm resistance.
NJU26220 - 5 - ver.2005-12-01 1. audio interface the serial audio interface carries audio data to and from the NJU26220. industry standard serial data formats of i 2 s, msb-first left-justified or msb-first right-justified ar e supported. table 2 shows pin description of input pin and output pin of NJU26220. table 2 serial audio input /output pin description pin no. symbol description 47 sdi0 46 sdi1 stereo l/r input (pin select) 45 sdi2 c/sw input 44 sdi3 sl/sr input 39 sdo0 monitor output 38 sdo1 l/r output 37 sdo2 c/sw output 36 sdo3 sl/sr output l/r: front channel, c/sw: center channel and sub woofer, sl/sr: surround channel.
NJU26220 - 6 - ver.2005-12-01 the NJU26220 has a pair of bit clock lines (bcki and bc ko) and a pair of left/right clock lines (lri and lro). the clock inputs bcki and lri are used to accept timi ng signals from an external device when the NJU26220 operates in slave mode. the clock outputs bcko and lro are pr ovided for delta-sigma a/d and d/a converters when the NJU26220 operates in master mode. in slave mode, the output of bcko and lro are the buffered output of bcki and lri. the mck always generates the sy stem clock supplied to the nj u26220 expect reset sequence. fig. 4 serial audio interface NJU26220 bcko lro mck bcki lri serial data outputs serial clock outputs serial clock inputs serial data inputs system clock for a /d, d/a converter s sdo0 sdo1 sdo2 sdo3 sdi0 sdi1 sdi2 sdi3
NJU26220 - 7 - ver.2005-12-01 2. host interface the NJU26220 can be controlled via serial host interfac e (shi) using either of two serial bus format: i 2 c bus or 4-wire serial bus. data transfers are in 8 bit packets (1 byte ) when using either format. the shi operates only in a slave fashion. a host controller connected to the interface always drives the clock (scl / sck) line and initiates data transfers, regardless of the chosen communication protocol. the sel pin controls the serial bus mode. when th e sel is low during the NJU26220 initialization, i 2 c bus is available. when the sel is high during the NJU26220 initiali zation, 4-wire serial bus is available. table 3 serial host interface pin description pin no. symbol (i 2 c / serial) i 2 c bus format 4-wire serial bus format 27 scl/sck serial clock serial clock 28 sda/sdout serial data serial data output 25 ad1/sdin i 2 c bus address bit1 serial data input 26 ad2/ssb i 2 c bus address bit2 slave select note: when i 2 c is selected, sda/sdout pin is a bi-directional open drain. sda/sdout pin, which is assigned for i 2 c, requires a pull-up resister. when 4-wire serial bus is selected, sda/sdout pin is cmos output. 2.1 i 2 c bus when the NJU26220 is configured for i 2 c bus communication in sel=?low?, the serial host interface transfers data on the sda pin and clocks data on the scl pin. sda is an open drain pin requiring a pull-up resistor. pins ad1 and ad2 are used to configure the seven-bit slave address of the serial host interface. this offers additional flexibility in a system design by offering two different possible slave addresses for which the NJU26220 will respond to. an address can be arbitrarily set up with an internal setup and these ad1/ad2 pins. . table 4 i 2 c bus slave address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 1 1 ad2* 1 ad1* 1 r/w *1 slave address is 0 when ad1 is ?low?. slave address is 1 when ad1 is ?high?. the figure on the following shows the basic timing relationsh ips for transfers. a transfer is initiated with a start condition, followed by the slave address byte. the sl ave address consists of the seven-bit slave address followed by a read/write (r/w) bit. when an address with an effective serial host interface is detected, the acknowledgement bit which sets a sda line to ? low? in the ninth bit clock cycle is returned.
NJU26220 - 8 - ver.2005-12-01 the r/w bit in the slave address byte sets the direction of data transmission until a stop condition terminates the transfer. r/w = ?low? indicates the host will send to the NJU26220 while r/w = ?high? indicates the host will receive data from the NJU26220. fig. 5 i 2 c bus format the serial host interface supports ?standard-mode (100kbps)? and ?fast-mode (400kbps)? i 2 c bus data transfer. 2.2 4-wire serial interface the serial host interface can be configured for 4-wire serial bus communication by setting sel=?high? during the reset sequence initialization. shi bus comm unication is full-duplex; a write byte is shifted into the sdin pin at the same time that a read byte is shifted out of the sdout pin. data transfers are msb first and are enabled by setting ssb=? low?. data is clocked into sdin on rising transitions of sck. data is latched at sdout on falling transitions of sck except for the first byte(msb) which is latched on the falling transitions of ssb. sdout is always cmos output. sdout does not require a pull-up resistor. 1-7 8 9 1-7 8 9 s p sda scl address data ack ack r/w start stop
NJU26220 - 9 - ver.2005-12-01 3. pin setting the NJU26220 operates default command setting after resetting the NJU26220. in addition, the NJU26220 restricts operation at power on by setting proc pin and muteb pin. these pins are input pin. however, these pins operate as bi-directional pins when test for internal. connect with vddio or vssio through 3.3k-ohm resistance. table 5 the function of a functional setting pin 4 watchdog clock the NJU26220 outputs clock pulse through wdc (pin no.8) during normal operation. the wdc clock is useful to check the status of the NJU26220 operation. for example, a microcomputer monitors the wdc clock and checks the status of the NJU26220. when the wdc clock pulse is lost or not normal clock cycle, the NJU26220 does not operate correctly. then reset the NJU26220 and set up the NJU26220 again. the wdc pin is open drain output. connect with vddio through 3.3k-ohm re sistance when wdc is useful. connect with vssio through 3.3k-ohm resistance when wdc is not useful. do not open wdc pin. note: the cycle of wdc output is rough. because wdc output inserts in the process of sound processing. in slave mode, when there is no input of bcki/lri, wdc can not output. it is required to set up a sampling rate correctly. pin setting function high the NJU26220 operates default setting after reset. proc low the NJU26220 does not operate after reset. sending start command is re q uired for startin g o p eration. high master volume is set 0db after reset. muteb low master volume is set mute after reset.
NJU26220 - 10 - ver.2005-12-01 5. NJU26220 command table host processor can control the NJU26220 via i 2 c bus interface or 4-wire serial bus. the following table summarizes the available user commands. no. command command description 1 set_task_cmd decode mode: pro logic ii, do lby virtual speaker, dolby headphone, pink noise generator, downmix, delay select, lfe generator 2 pro2mode_cmd mode setting: pro logic ii (movie, music etc.,), panorama mode 3 pro2cdcfg_cmd dimension sett ing, center width control 4 pro2flags_cmd mode setting: auto balance, 3 stereo, phantom center etc., 5 dvs_dh_cmd dvs/dh sele ct, dvs output speaker layout, dvs/dh output mode 6 samplerate_cmd 32.0khz, 44.1khz, 48.0khz 7 png_mode_cmd pink noise generator output channel configuration 8 delay_cmd delay time at center and surround channel 9 gain_cmd each channel trimmer 10 system_state_cmd serial audio inte rface format, clock, master/slave 11 watchdog_cmd watchdog clock interval 12 smooth_cmd smooth control time 13 output_sel_cmd output select 14 lfe_config_cmd lfe cutoff frequency select 15 reinit_cmd re-initialization command 16 software_reset_cmd software reset 17 start_cmd start command at power on 18 nop_cmd nop command license ?dolby?, ?pro logic ii?, ?dolby virtual speaker?, ?dolby h eadphone? and the double-d symbol are trademarks of dolby laboratories. the NJU26220 may only be supplied to licensees of or companies authorized by dolby laboratories. please refer all licensing inquirie s to dolby laboratories. ver. 1.01 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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